1. Technical Field
The present disclosure relates to an amplifier device comprising a digital modulator and a power circuit.
The present disclosure relates in particular to amplifiers comprising a digital delta-sigma modulator and a power circuit in class D.
2. Description of the Related Art
These last years, D-class amplification has known a significant development due to the need of making compact power amplifiers offering an energy efficiency very much higher than the efficiency offered by conventional AB-class amplifiers, which usually do not exceed 30%. Thus, a D-class amplifier easily offers 90% efficiency and thus only wastes 10% of the energy it consumes, vs. 70% of wasted energy in an AB-class amplifier. This is due to the fact that D-class amplifiers are chopper amplifiers, operating by MOS transistors switching and therefore consuming energy only during the switching periods.
FIG. 1A shows a conventional architecture of D-class amplifier. The amplifier comprises a modulator 1 which input receives a signal to be amplified IS and which output controls a power circuit PA in D-class. The output of the power circuit PA supplies an output signal OS to a load LD, for example a speaker.
The power circuit PA in D-class usually comprises MOSFET transistors arranged according to the “totem pole” mounting. It is a chopper circuit which supplies a square signal OS having the shape of a voltage square wave oscillating between two voltages +Vcc and −Vcc. In audio applications, the conversion of the output signal OS into analog audio signal is performed either by means of a low-pass filter LPF of LC type arranged between the output of the power circuit PA and the load LD, or by letting the load filter the output signal (mounting called “filterless”).
Numerous D-class amplifiers are equipped with a pulse width modulator of PWM type. Others comprise a delta-sigma modulator supplying a pulse density modulated signal or PDM. A delta-sigma modulator has the advantage of performing a noise shaping which consists in rejecting the quantification noise in the field of high frequencies, outside the useful band, thanks to a feedback of the output on the input of the modulator and providing a high sampling frequency in relation to the bandwidth of the input signal.
In compensation for their advantageous efficiency, D-class amplifiers usually offer performances which are very much lower than those of AB-class amplifiers. An AB-class amplifier may easily have a total harmonic distortion THD of around 90 dB and a signal to noise ratio SNR of 100 dB whereas a D-class amplifier hardly reaches a THD of 40 dB and a SNR of 80 dB. Despite the noise shaping performed by the delta-sigma modulator, the defects inherent to the power circuit are not suppressed because they are generated downstream from the modulator, and cause a significant increase of the distortion and noise rates in the output signal.
The U.S. Pat. No. 5,777,512 of the company Tripath Technology discloses a D-class amplifier comprising a continuous-time delta-sigma modulator operating at high frequency (1.5 MHz). The output signal supplied by the power circuit is sent in a state loop of the delta-sigma modulator through an anti-aliasing filter and a continuous-time gain circuit.
Continuous-time or discrete time delta-sigma modulators (switch capacitance modulators, technique called “switch cap”) raise stability issues with architectures of order higher than 2. Now, it may hardly be hoped to obtain audio performances comparable to those of AB-class amplifiers with a 1 or 2 order delta-sigma modulator, unless making a modulator of high complexity and expensive to implement.
The present disclosure relates to amplifiers comprising a digital delta-sigma modulator. FIG. 1B shows a conventional architecture of digital delta-sigma modulator 1. The modulator 1 is here of 3 order and comprises three delta-sigma stages DSa, DSb, DSc and a quantifier QT. Each delta-sigma stage comprises an input adder Sa, Sb, Sc which output drives an integrator ITa, ITb, ITc. The positive input of the adder Sa of the delta-sigma stage DSa receives the input signal IS, the positive input of the adder Sb of the delta-sigma stage DSb receives the output of the integrator ITa and the positive input Sc of the delta-sigma stage DSc receives the output of the integrator ITb. The integrator ITc supplies to the quantifier a signal NSS and the quantifier QT supplies a quantified signal QS. The signal QS is sent to the negative input of the adder Sa through a state loop SLa, to the negative input of the adder Sb through a state loop SLb, and to the negative input of the adder Sc through a state loop SLc. The quantification noise is conventionally shaped by applying to the integrators ITa, ITb, ITc a clock signal having a frequency Fs much higher than the bandwidth of the input signal IS, generally higher than one Megahertz for an audio signal in the range 30 Hz−20 KHz. The quantified signal QS is applied to the power circuit PA. The latter supplies the output signal OS oscillating between +Vcc and −Vcc which is applied to the load LD, possibly through a low-pass filter LPF.
A major issue in the manufacture of a digital amplifier is to correct the defects introduced into the output signal OS by the power circuit PA. Such defects are called “non-idealities” and generate distortion and noise.
Various solutions have been suggested to that end. The technique usually retained consists in sending an error signal in the delta-sigma modulator. This error signal is for example elaborated by calculating a difference between an ideal square wave and the square wave supplied by the power circuit PA.
In particular, the U.S. Pat. No. 6,373,334 describes in relation with the FIGS. 2A, 9 thereof a digital delta-sigma modulator which delta-sigma stages receive two types of feedback signals, i.e. a signal taken from the output of the quantifier (“a priori feedback”) and an error signal (“real time feedback”) which is previously converted into digital signal by an analog to digital converter. The error signal is generated by comparing the signals supplied by the power circuit when it is connected to a load, to “ideal” signals supplied by reference switches which simulate the ideal operation of the power circuit in the absence of load.
It may be wished to provide an alternate technique allowing a digital amplifier to be conferred satisfying performances in terms of distortion, signal to noise ratio and efficiency.
The present disclosure also relates to audio codecs (compression-decompression circuits). Audio codecs generally comprise, on the same semiconductor chip, one or more amplifiers, analog to digital converters to convert external analog signals into digital signals, and signal process processors or DSP to convert into amplifiable audio signals digital audio data received or read in compressed or coded form and vice-versa. It may be wished to improve the structure of these codecs so as to decrease the complexity and cost thereof.
The present disclosure more generally relates to the noise reduction in digital modulators. It is known that digital modulators generate a quantification or sampling noise which is constant and independent of the signal, and which depends of the quantification or sampling step and the quantification or sampling frequency. Although this noise is in the order of the least significant bit of the modulated signal, its impact on the signal to noise ratio is all the more significant as the signal is low. It may thus be wished to provide a technique allowing the influence of the noise on low-amplitude signals to be reduced.